The present invention relates to a multilayer printed wiring board having a filled-via structure in which an upper via hole is formed directly above a lower via hole.
The so-called build-up multilayer printed wiring board, shown in FIG. 11(A), consists of a via hole 650 that electrically connects a lower conductor circuit 634 and an upper conductor circuit 652 to each other. The via hole 650 is formed as such that a plated film 648 is created on the inner surface of an opening 642 which is formed in an interlaminer resin insulating layer 640. The inside portion of the plated layer 648 for forming the via hole 650 is filled with resin 660a in order to create an upper interlaminer resin insulating layer 660. Therefore, if a via hole is formed above the via hole 650 as indicated by a dashed line shown in the drawing, the resin 660a enclosed under the plated layer 648 inhibits easy establishment of a connection between the two via holes.
Therefore, when a via hole is formed on a lower via hole, that is, when a via hole is directly connected to another via hole without any interposition of wiring in order to raise the density, a so-called filled-via structure is employed to form the multilayer printed wiring board. As shown in FIG. 11 (I), the filled-via structure is formed such that an opening 542 in the interlaminer resin insulating layer 540 is filled with plated metal 548. The foregoing technique has been disclosed by the applicant of the present invention in Japanese Patent Laid-Open No. 2-188992, Japanese Patent Laid-Open No. 3-3298 and Japanese Patent Laid-Open No. 7-34048.
A method of forming a via hole on another via hole will now be described with reference to FIG. 20(B) to FIG. 11(I).
Initially, the upper and lower surfaces of a substrate 530 having a surface on which a conductor circuit 534 has been formed are coated with resin 540 for creating a lower interlaminer resin insulating layer (see FIG. 11(B)). An opening 542 for forming a via hole is then formed in the resin 540 (see FIG. 11(C)). Subsequently, an electroless-plated film 544 is uniformly deposited on the surface of the substrate 530, and then a resist film 546 is formed (see FIG. 11(D)). This is proceeded by electrolytically-plated film 548 being deposited on a portion in which the resist film 546 is not formed. Thus, a via hole 550 and a conductor circuit 552 are formed (see FIG. 11(E)). The resist film 546 and the electroless-plated film 544 below the resist film 546 are then separated. Subsequently, the surface of the substrate 530 is coated with resin 560 which becomes the upper interlaminer resin insulating layer (see FIG. 11(F)). This is followed by photoetching being performed to make an opening 562 in preparation for an upper via hole in the interlaminer resin insulating layer 560 (see FIG. 11(G)). Then, an electroless-plated film 564 is uniformly deposited on the surface of the substrate 530, and then a resist layer 566 is formed. An electrolytically-plated film 568 is then deposited in the portion in which the resist layer 566 is not formed (see FIG. 11M). Finally, the resist layer 566 and the electroless-plated film 564 below the resist layer are separated so that a via hole 570 and a conductor circuit 572 are formed (see FIG. 11W).
However, the multilayer printed wiring board manufactured by the above-mentioned manufacturing method is subject to unsatisfactory reliability of the connection established between the lower via hole 550 and the upper via hole 570. The inventor of the present invention has researched the cause of this unsatisfactory reliability, resulting in the discovery that a recess 550a is formed in the central portion of the via hole 550 when the electrolytically-plated film 548 is deposited in the opening 542 which is formed in the interlaminer resin insulating layer 540, as shown in FIG. 11(E). That is, as shown in FIG. 11(F), when resin 560, which will be formed into the upper interlaminer resin insulating layer, has been applied to the portion above the via hole 550, the thickness h1 of the resin 560 in the via recess 550a and thickness h2 of the portion except for the recess 550a, are different from each other. Therefore, when the opening 562 for forming the via hole is created in the interlaminer resin insulating layer 560 by photoetching, a small quantity of resin 560a is left in the recess 550a as shown in FIG. 11(G). That is, as shown in FIG. 11(I), the resin 560a insulates the connection. The result of which being that, satisfactory reliability of the connection between the lower via hole 550 and the upper via hole 570 cannot be realized.
In addition to resin 560a in the recess 550a, a further occurrence has been detected that, due to the dint caused by the oxidized film, the reliability of the connection between the lower via hole 550 and the upper via hole 570 is deteriorated. That is, as shown in FIG. 11(E), when the via hole 550 has been formed with the use of electrolytically-plated film 548, an oxidized film is formed on the surface of the lower via hole 550. As shown in FIG. 11(J), the interlaminer resin insulating layer 560, which repeats thermal contraction, imposes stress in a direction to cause the lower via hole 550 and the upper via hole 570 to be separated from each other. If an oxidized film is formed in the interface between the lower via hole 550 and the upper via hole 570, that is, on the surface of the lower via hole 550, the surface of the lower via hole 550 and the lower surface of the upper via hole 570 are separated from each other. As a result, the electric connection between the lower via hole 550 and the upper via hole 570 is broken.
The filled-via multilayer printed wiring board has another problem. Since recesses 550a and 570a are formed in the upper surfaces of the via holes 550 and 570, each having the above-mentioned filled-via structure as shown in FIG. 11(J), the smoothness of the surface of the substrate is deteriorated. Therefore, the mounting reliability that is required when an IC chip or the like is mounted is sometimes deteriorated. To improve the smoothness of the substrate, in order to overcome the above-mentioned problem, the applicant of the present invention has discovered a technique for smoothing the upper surfaces of the via holes. That is, as shown in FIG. 12(D), the upper surfaces of the lower via hole 550 and the upper via hole 570 are flattened so that the substrate is smoothed. FIG. 12(E) is a horizontal cross sectional view taken along line Exe2x80x94E shown in FIG. 12(D), that is, FIG. 12(E) shows a conductor layer formed on the interlaminer resin insulating layer 540. FIG. 12(D) is a vertical cross sectional view taken along line Dxe2x80x94D shown in FIG. 12(E).
However, if the upper surface of the via hole is flattened, the upper interlaminer resin insulating layer 560 above the plane layer 553 as shown in FIG. 12(E) is raised as shown in FIG. 12(D). Therefore, in a multilayer printed wiring board having a conductor layer in which a conductor pattern 552 and a plane layer 553 concur, it has been established that the surface of the substrate cannot be flattened.
The reason why the upper layer of the plane layer 553 is raised will now be illustrated with reference to FIGS. 22(A), 22(B), 22(C) and 22(D) showing a process for manufacturing a multilayer printed wiring board. As shown in FIG. 12(A), both the conductor pattern 552, and the plane layer 553, are formed on the upper surface of the lower interlaminer resin insulating layer 540 as described above with reference to FIG. 12(E). To form the upper interlaminer resin insulating layer as shown in FIG. 12(B), the surface of the substrate is coated with resin 560, which will be molded into an interlaminer resin insulating layer with the use of a roll coater or the like. However, the thickness of the upper portion of the plane layer 553 is undesirably enlarged even if the resin 560 is made to have a uniform thickness. The reason for this will now be considered. Resin is introduced between the, conductor pattern 552 and the via hole 550A (see FIG. 12E). Therefore allowing the portion around the conductor pattern 552 and the via hole 550A, which is connected the conductor pattern 552, to be flattened. However, as the resin 560 cannot be relieved from the portion above the plane layer 553, the interlaminer resin insulating layer is undesirably expanded.
Then, as shown in FIG. 12(C), an opening 562 for forming the upper via hole is made in the resin 560. As shown in FIG. 12(D), the opening 542 is then filled with plated metal 568 so that an upper via hole 570 is formed.
However, the multilayer printed wiring board containing the flattened upper surface structured via holes as shown in FIG. 12(D), has a flaw in that the interlaminer resin insulating layer 560 easily separates. The interlaminer resin insulating layer 560 made of resin has excellent adhesiveness with respect to the lower interlaminer resin insulating layer 540 made of resin. However, the interlaminer resin 25 insulating layer 560 has insufficient adhesiveness with respect to the conductor pattern 552, the via hole 550A, and the plane layer 553 made of metal materials. Since the upper interlaminer resin insulating layer 560 is directly in contact with the lower interlaminer resin insulating layer 540 in the section around the conductor pattern 552 and the via hole 550B, strong adhesive contact can be effectuated. In the plane layer 553, the upper interlaminer resin insulating layer 560 cannot be brought into direct contact with the lower interlaminer resin insulating layer 540, resulting in inadequate adhesiveness. Thus, separation of the interlaminer resin insulating layer 560 is precipitated. The multilayer printed wiring board described with reference to FIG. 11(J) is free from the problem of separation. It can be considered that the reason for this lies in the recess in the via hole which is formed in the plane layer. The recess can be said to have an anchoring effect for the interlaminer resin insulating layer.
Solder bumps are created on the surface of a printed wiring board, such as a package substrate, in order to establish an electric connection to an electronic element, such as an IC chip, which will be mounted. Solder bumps are constructed on the conductor circuit on the surface of the substrate. In addition, solder bumps are sometimes created on the via hole in order to, for example, raise the degree of integration. A process for forming solder bumps on a printed wiring board will now be described with reference to FIG. 13.
FIG. 13(A) shows the cross section of a conventional multilayer printed wiring board 510. The multilayer printed wiring board has a structure comprising conductor circuits 534, 552 and 572, which are formed on the upper and lower layers of a core substrate 530 through a plurality of interlaminer resin insulating layers 540 and 560. An opening 562 for the via hole is made in the outermost interlaminer resin insulating layer 560. A via hole 570 is then formed in the opening 562 with copper plating. The via hole 570 establishes the connection to the lower conductor circuit 552 formed below the interlaminer resin insulating layer 560. Resists 580 with openings 581 each having a predetermined diameter, are formed in the outermost interlaminer resin insulating layer 560.
When solder bumps are established on the multilayer printed wiring board 510, a metal mask 598 is placed on the multilayer printed wiring board 510, as shown in FIG. 13(B). Subsequently, solder paste is printed on the surfaces of the openings 581 in the plating resist 580. The metal mask 598 has openings 598a and 598b formed in positions corresponding to the positions of the openings 581 formed in the plating resist 580. The opening 598b corresponding to the via hole 570 has a relatively large diameter, while the opening 598a corresponding to the conductor circuit 572 has a relatively small diameter. As a result, solder paste can be printed on the surface of the via hole 570 in a larger quantity.
After solder paste has been printed, the multilayer printed wiring board 510 is allowed to pass through a heating furnace. Thus, the solder paste is allowed to ref low so that solder bumps 588 are formed, as shown in FIG. 13(C). Thereafter, fluxes that flow from the solder during the reflow process are cleaned. An IC chip 590 is then mounted on the multilayer printed wiring board 510 in such a manner that the IC chip""s solder pads 592 correspond to the solder bumps 588 adjacent to the multilayer printed wiring board 510. Subsequently, the multilayer printed wiring board 510 is allowed to pass through a heating furnace so that the solder pads 588 are melted. Thus, the multilayer printed wiring board 510 and the IC chip 590 are electrically connected to each other. At this time, the fluxes allowed to flow from the solder when the reflow process was performed are cleaned.
However, the above-mentioned multilayer printed wiring board has proven to be inadequate in that appropriate connection to an IC chip cannot always be established. That is, the height h3 of the solder bumps 588 formed on the recessed via hole 570, and the height h4 of the solder bumps 588 formed on the flat conductor circuit 572, cannot easily be made to be the same, as shown in FIG. 13(C). Therefore, any one of the solder bumps 588 adjacent to the multilayer printed wiring board 510 cannot appropriately be connected to the solder pads 592 adjacent to the IC chip 5590, as shown in FIG. 13(D).
Moreover, the metal mask must have openings 598a and 598b having different diameters which are formed at positions corresponding to the positions of the openings 581 formed in the plating resist 580, as described with reference to FIG. 13(B). Therefore, adjustment cannot easily be performed. As described above, solder is allowed to reflow for the purpose of forming the solder bumps, and then the connection between the solder bumps on the multilayer printed wiring board, and the solder pads on the IC chip, is established by performing the reflow process. Finally, the fluxes discharged from the solder must be cleaned. Since the via hole 570 has been filled with solder, the quantity of solder is increased, resulting in the quantity of seepage of fluxes also being increased. Therefore, fluxes are residual even after the cleaning process has been completed, causing short circuit of the wiring to sometimes occur. In addition to the above-mentioned shortcomings, when the reflow process is performed, the multilayer printed wiring board 510 is sometimes warped. In this case, the reliability of mounting of the IC chip 190 sometimes deteriorates.
To counteract the aforementioned imperfections, an object of the present invention is to provide a multilayer printed wiring board having a filled-via structure and exhibiting excellent reliability of the connection between via holes.
Another objective of the present invention, is to provide a multilayer printed wiring board with which the surface of a substrate thereof can be flattened and which is capable of preventing delamination of the interlaminer resin insulating layer.
Another object of the present invention is to provide a multilayer printed wiring board having excellent reliability of the connection with solder bumps.
In order to achieve the aforementioned objectives, the present invention provides a multilayer printed wiring board containing interlaminer resin insulating layers and conductor circuits manufactured as such, that the interlaminer resin insulating layers and the conductor circuits are alternately stacked, wherein an opening is formed in a lower interlaminer resin insulating layer which is filled with a plated metal layer so that a lower via hole having a flat surface is formed. Subsequently allowing for an upper via hole to be formed above a lower via hole.
The present invention is structured in a manner which avoids residual resin. This is made possible by the via hole having a flat surface when the opening for forming the upper via hole is formed within the interlaminer resin insulating layer. Therefore, reliability of the connection between the lower via hole and the upper via hole can be maintained. Since the lower via hole has the flat surface, the smoothness and flatness of the multilayer printed wiring board can be maintained even when an upper via hole is superimposed on the lower via hole.
One of the features of the present invention is that, the surface of the lower via hole is subjected to a coarse process. Therefore, even if an oxidized film is placed on the foregoing surface, the reliability of the connection between the lower via hole and the upper via hole can be maintained.
Another aspect of the present invention is that, the side surface of the opening in the lower interlaminer resin insulating layer is subjected to a coarse process, resulting in improved adhesiveness with the via hole created in the opening.
In conjunction with the above, the present invention submits the surfaces of the upper via hole and the conductor circuit to the coarse process. Therefore, the adhesiveness between the upper via hole, and solder pads on the conductor circuit or an interlaminer resin insulating layer, can be improved.
With respect to the present invention, the lower interlaminer resin insulating layer is made of a composite material of thermoplastic resin and thermosetting resin or mostly comprised of thermoplastic resin which has great tenacity. The durability of this new resin composition prevents the occurrence of cracks in the interlaminer resin insulating layer, even if the opening in the interlaminer resin insulating layer is lined with plated metal for a via hole.
According to another aspect of the present invention, the ratio of the diameter of the via hole and the thickness of the interlaminer resin insulating layer is larger than 1. That is to say, the depth of the opening for the via hole is not too large with respect to the diameter of the opening. Therefore, plating solution can sufficiently be introduced into the opening during the process of forming the via hole with use of a plating process. Moreover, the ratio of the diameter of the via hole and the thickness of the interlaminer resin insulating layer is 4 or lower. That is, the diameter of the opening for the via hole is not too large with respect to the depth of the opening. Therefore, adjustment of the plating duration enables the surface of the via hole to be flattened and smoothed.
In order to achieve the above purpose, the present invention provides a multilayer printed wiring board comprising of interlaminer resin insulating layers and conductor circuits, manufactured as such that the interlaminer resin insulating layers and the conductor circuits are alternately stacked, wherein an opening is formed in a lower interlaminer resin insulating layer. The opening is filled with a plated metal layer so that a lower via hole is formed, and an upper via hole is formed above a coarse layer formed on the surface of the lower via hole.
According to another aspect of the present invention, the lower via hole and the upper via hole are connected through a coarse processed layer formed on the surface of the lower via hole. Therefore, even if an oxidized film is formed on the surface of lower via hole, the reliability of the connection between the lower via hole and the upper via hole can be maintained.
Additionally, the present invention has a recess which is formed in the central portion of the lower via hole. Accordingly, a coarse layer is formed to be perpendicular to the recess, thus allowing the lower via hole and the upper via hole to be firmly connected to each other. The reliability of the connection between the lower via hole and the upper via hole can thus be maintained.
In conjunction with the above, the side surface of the opening of the lower interlaminer resin insulating layer is subjected to a coarse process. Therefore, the adhesiveness with the via hole formed in the opening can be improved.
According to another aspect of the present invention, the surfaces of the upper via hole and the conductor circuit are subjected to the coarse process. Therefore, the adhesiveness between the upper via hole and solder pads, formed on a conductor circuit or an interlaminer resin insulating layer, can be improved.
The present invention has a the lower interlaminer resin insulating layer which is made of a composite material of thermoplastic resin and thermosetting resin or mainly made of thermoplastic resin which has great tenacity. Therefore, even if the opening in the interlaminer resin insulating layer is filled with plated metal for a via hole, a crack does not easily occur in the interlaminer resin insulating layer.
According to another aspect of the present invention, the ratio of the diameter of the via hole and the thickness of the interlaminer resin insulating layer is larger than 1. That is, the depth of the opening for forming the via hole is not too large with respect to the diameter of the opening. Therefore, plating solution can sufficiently be introduced into the opening during the plating process used for forming the via hole. Therefore, the via hole can efficiently be formed by the plating process.
In order to achieve the above purpose, the present invention provides a multilayer printed wiring board having, interlaminer resin insulating layers and conductor layers manufactured as such that the interlaminer resin insulating layers and the conductor circuits are alternately stacked, wherein at least one of the conductor layers has a plane layer comprising of a conductor pattern, which is connected to a the lower via hole. The via hole which is connected to the conductor pattern is filled with a plated metal layer so that the surface of the via hole is flattened, and the via hole formed in the plane layer is filled with a plated metal layer allowing for a recess to be formed in the surface of the via hole formed in the plane layer.
The present invention is structured as such that a recess is provided for the via hole formed within the plane layer. The recess serves as an anchor to improve the adhesiveness between the plane layer and the upper interlaminer resin insulating layer. Therefore, separation of the interlaminer resin insulating layer can be prevented. When resin for forming the interlaminer resin insulating layer above the plane layer is applied in the manufacturing process, the resin is relieved into the recess of the via hole formed in the plane layer. As a result, the surface of the interlaminer resin insulating layer, that is, the surface of the multilayer printed wiring board can be flattened. Thus, the mounting reliability when an IC chip or the like is mounted can be improved. Since the via hole which is connected to the conductor pattern has a flat surface, the smoothness and flatness of the multilayer printed wiring board can be maintained even if the via hole is superimposed on the via hole which is connected to the conductor pattern.
According to another aspect of the present invention, the side surface of the opening of the interlaminer resin insulating layer is subjected to a coarse process. Therefore, the adhesiveness with the via hole formed in the opening can be improved.
Another feature of the present invention pertains to, the surface of the plane layer, including the via hole, being subjected to a coarse process. Therefore, the reliability of the connection between the surface and the upper interlaminer resin insulating layer is not affected.
According to another aspect of the present invention, the depth of the recess provided for the via hole formed in the plane layer is 5 xcexcm or greater. Therefore, a satisfactory anchoring effect can be obtained, allowing the adhesiveness between the plane layer and the upper interlaminer resin insulating layer to be improved. As a result, separation of the interlaminer resin insulating layer can be prevented. When resin for forming the interlaminer resin insulating layer above the plane layer is applied during the manufacturing process, the resin can be relieved into the recess provided for the via hole formed in the plane layer. As a result, the foregoing interlaminer resin insulating layer can be flattened. The depth of the via hole positioned in the plane layer being 50 xcexcm or smaller, allows for the surface of the via hole, which is connected to the conductor pattern to be flattened.
According to another aspect of the present invention, the area of the plane layer is 0.01 dm2 to 10 dm2. Therefore, a recess can be formed on the surface of the plated metal enclosed in the via hole positioned in the plane layer. Moreover, the surface of the plated metal enclosed in the via hole which is connected to the conductor pattern can be flattened.
In order to achieve the above purpose, the present invention provides a multilayer printed wiring board incorporating interlaminer resin insulating layers and conductor circuits manufactured as such that the interlaminer resin insulating layers and the conductor circuits are alternately stacked. The multilayer printed wiring board incorporates, solder bumps formed on a conductor circuit formed on the outermost interlaminer resin insulating layer, and solder bumps formed on a via hole created with the use of an enclosing plated metal layer in an opening formed in the outermost interlaminer resin insulating layer.
In the present invention, a plated metal layer is enclosed in the opening made for the via hole. Thus, the height of the surface of the via hole is made to be the same as the height of the conductor circuit on which solder bumps are formed. Therefore, when solder paste in the same quantities is printed onto the via hole and the conductor circuit, the heights of the solder bumps formed on the via hole and the solder bumps formed on the conductor circuit can be made to be the same, resulting in an improvement in the reliability of the connection of the solder bumps.
According to another aspect of the present invention, a recess is formed in the central portion of the via hole. Therefore, the via hole and the solder bumps can firmly be connected to each other, improving the reliability of the solder bumps.
In addition to the above, the side surface of the opening of the outmost interlaminer resin insulating layer is subjected to a coarse process, allowing the adhesiveness with the via hole formed in the opening 5 to be improved.
According to another aspect of the present invention, the surfaces of the via hole and the conductor circuit are subjected to the coarse process. Therefore, the adhesiveness between the via hole, the conductor circuit, and solder bumps formed thereon, can be improved.
Subsequently, solder bumps are, with noble metal, formed on the surface of the via hole created by enclosing plated metal. Therefore, no oxidized film is formed between the surface of the via hole made of copper or the like and the solder bumps. Thus, the adhesiveness between the via hole and the solder bumps can be improved.